Users typically design logic circuits using a computer with a schematic capture computer program or a hardware description language (HDL). The program allows the user to place symbols onto a computer screen and interconnect the symbols to indicate a circuit diagram, or to describe circuits and connections using textual description. The computer then captures the schematic diagram or logic design. Schematic capture and HDL entry are processes of converting a schematic drawing or text file generated by a user into a format which can be processed by a computer. Schematic capture and HDL software packages make it possible for a user to communicate the design to a computer conveniently. A schematic capture package typically converts the interconnected set of functional components to a net list (list of components and interconnections between these components) which can be further manipulated by other computer programs to perform a function desired by the user.
Typical schematic capture packages have included a library of primitive components, such as Boolean AND, XOR, flipflop, etc., which the user may place onto a computer display and interconnect with lines to form a logic design. However, users frequently think in terms of high-level functions to be performed, for example, counters, adders, registers and multiplexers. Entering a design directly in terms of the higher level logic operations the user intends to perform is more convenient and intuitive for a user than entering the logic design in terms of primitive AND, flipflop gates, etc.
Designing with Bus-Wide Functions
Users frequently design with bus-wide functions. For example, when a user manipulates a 10-digit number, the digits of the number are placed on a bus and are processed (added, compared, stored) as multi-bit numbers. In the past, the user may have been required to perform repetitive operations to generate the logic for processing the multiple bits. If the precision of the arithmetic to be performed changes, the user must then redesign a circuit to change-the width of the bus. Such activities become tedious and time-consuming for the user. It is desirable to perform repetitive operations automatically.
Certain high level arithmetic functional components such as adder, register, and counter are frequently used. Also used are high level register functions such as data registers, parallel-in serial-out shift registers, serial-in parallel-out shift registers, and left-right shift registers. Related patent application Ser. No. 08/268,884, filed concurrently with the present application, now U.S. Pat. No. 5,499,192 entitled METHOD FOR GENERATING LOGIC MODULES FROM A HIGH LEVEL BLOCK DIAGRAM, U.S. Pat. No. 5,499,192 describes a method for implementing certain high-level functional components directly input by a user in a logic array chip without involving the user in the intermediate step of generating primitive functional components.
Resource Allocation
The eventual placement of the elements of a logic design into a chip which will implement the design depends upon the resources provided in the chip and the distribution of these resources. For efficiency it is important that the resources of the chip be considered in allocating logic of the design into the chip, so that the logic functions can be computed at high speed, the area needed can be minimized, and the greatest amount of logic can be packed into a chip of a given size. Such resource allocation is discussed more thoroughly in copending U.S. patent application Ser. No. 07/784,842, which has been incorporated herein by reference.
Use With Xilinx-4000 Architecture
Xilinx XC4000-series field programmable gate array chips offer several resources intended for special purposes:
For each of these resources it is necessary to evaluate the user's logic design and place logic such that the above resources are efficiently used.
FIG. 5 shows a portion of a Xilinx 4000-series field programmable logic array chip which can be advantageously programmed using the methods of the invention. Such chips are further described in the Xilinx Technical Data book entitled XC 4000 Logic Cell.TM. Array Family. .COPYRGT. 1990 by Xilinx, Inc., and available from Xilinx, Inc. 2100 Logic Drive, San Jose, 95124, and incorporated herein by reference. These XC4000-series chips include logic blocks in the interior of the chip each of which include both combinatorial and sequential elements, and which include a fast carry circuit for implementing arithmetic functions in adjacent logic blocks. The chip includes interconnect lines of both short and long length, short for interconnecting nearby elements, and long for interconnecting elements in distant parts of the chip or for interconnecting multiple elements.